FIG. 1 is a circuit diagram which shows only the required components of a conventional nonvolatile semiconductor memory. Only those components that are necessary for explanation of data reading operation, program verification operation and erase verification operation are shown in this figure.
The nonvolatile semiconductor memory device shown in FIG. 1 includes a memory cell array 20 having a plurality of memory cells (also called as reading cell) disposed in a grid fashion, a row decoder 22, and bit lines 21 at the drain side and bit lines 23 at the source side. The memory cells store data. The row decoder 22 can select one row of the memory cells. That is, the row decoder 22 can select one of the word lines WL0 to WLn. The bit lines 21 and the bit lines 23 can selects a column of the memory cells of the memory cell array 20 based on a column signal input from a not shown column decoder.
Further, a reference cell 30 in the nonvolatile semiconductor memory device decides a storage state of the data at the time of reading the data. The reference cell 30 also carries out the operations like program verification and erase verification. Further, a sense amplifier 40 compares the signals output from the memory cell array 20 with the signals output from the reference cell 30.
Further, a reference word line driver 32 applies voltages corresponding to data reading operation, program verification operation, and erase verification operation respectively to a control gate of the reference cell 30. A reading voltage generator 24 generates a voltage required for reading the data. A program verification voltage generator 26 generates a voltage required for the program verification. An erase verification voltage generator 28 generates a voltage required for the erase verification.
Capacitance is intentionally generated at the bit lines 23 at the source of the memory cell array 20 and at the bit lines at the source of the reference cell 30 although no capacitors have been specifically shown in the figure. These capacitors are charged based on the signal output from the memory cell array 20. A sense amplifier 40 detects a potential difference based on a difference between charging speeds of these capacitors. The operation of the sense amplifier 40 will be explained later. Data reading operation, program verification operation and erase verification operation are performed based on the detected potential difference. Usually, these capacitors are provided in parallel to two input lines within the sense amplifier 40 respectively.
The reading cells or the reference cell 30 is electrically rewritable nonvolatile semiconductor memory such as, for example, an EEPROM (Electrically Erasable and Read-Only Memory) or the like. This nonvolatile semiconductor memory consists of a floating gate covered with an insulator and disposed between a source and a drain formed as n-type diffusion layers on a p-type silicon substrate, and a control gate for injecting a hot electron into the floating gate and for controlling a gate voltage.
The data reading operation, the program verification operation and the erase verification operation by the nonvolatile semiconductor memory device will be explained in this order. Data writing (that is, programming) is carried out based on, for example, a source voltage Vs=0 [V], a drain voltage Vd=5 to 6 [V] and a control gate voltage Vcg=12 [V] (that is, program voltage), and by injecting a hot electron into the floating gate from the drain.
Data erasing (that is, erasing) is carried out based on, for example, a source voltage Vs=5 [V] (that is, power source voltage) and a control gate voltage Vcg=-8.5 [V] (that is, erase voltage), with the drain in an open state, and by extracting an electron from the floating gate into the source.
Data Reading Operation:
During the data reading operation, p-type MOS transistors Tr11 and Tr21 are made ON using the signals PD1 and PD2 respectively.
The address of a cell to be read is specified as follows. That is, the not shown column decoder turns ON the MOS transistors connected to the bit line 21 at the drain side and the bit line 23 at the source side respectively (thus a bit line is selected), and the row decoder 22 applies a reading voltage supplied from the reading voltage generator 24 to the control gate of the reading cell (thus a word line is selected).
Thus, a reading cell from which data is to be read out is selected or specified by selecting a bit line and a word line corresponding to that cell. After the reading cell is selected, the MOS transistors Tr12 and Tr13 are made ON with a column selection signal CS. As a result, the selected bit line becomes valid, and it becomes possible to read the data stored in the reading cell.
On the other hand, with respect to the reference cell 30, there are disposed MOS transistors Tr22, Tr23, Tr25 and Tr26 having characteristics similar to those of the MOS transistors that are controlled in the operation of the reading cell. These transistors are disposed by taking into consideration characteristics of currents that are input into the sense amplifier 40 during the data reading operation, program verification operation and erase verification operation respectively. These MOS transistors are always ON.
The reference word line driver 32 applies a reading voltage supplied from the reading voltage generator 24, to the control gate of the reference cell 30 via a word line WLref, along the operation of the memory cell array 20.
In the memory cell array 20 and the reference cell 30 both, the MOS transistors Tr14 and Tr24 are turned ON by a signal EQ, and electric charges stored in the capacitors are discharged (reset). The signal EQ is again input into these transistors at a suitable timing due to which these transistors turn OFF.
Thus, a signal output from the bit line 23 at the source of the memory cell array 20 is input as a signal SAIN into the sense amplifier 40 via the MOS transistor Tr13. This signal SAIN represents a change of the electric potential of the capacitor as explained above.
In the reference cell 30, a signal output from the bit line at the source side is input as a signal SAREF into the sense amplifier 40. This signal SAREF also represents a change of the electric potential of the capacitor as explained above.
The sense amplifier 40 detects a change in the potential between the signal SAIN and the signal SAREF. In other words, the sense amplifier 40 detects a speed of charging to each of the above mentioned capacitors, thereby to calculate a difference in the potential between the signal SAIN and the signal SAREF.
For example, consider a case where the charging speed of the capacitor corresponding to the memory cell array 20 is lower than the charging speed of the capacitor corresponding to the reference cell 30 and that the potential of the signal SAIN is smaller than the potential of the signal SAREF at a timing when the MOS transistor Tr15 is turned ON with a signal LT. In this case the sense amplifier 40 decides that hot electrons have been injected into the floating gate, and outputs data "0" as a signal OUT.
On the other hand, when the charging speed of the capacitor corresponding to the memory cell array 20 is higher than the charging speed of the capacitor corresponding to the reference cell 30, and when the potential of the signal SAIN is larger than the potential of the signal SAREF at a timing when the MOS transistor Tr15 is turned ON with the signal LT, the sense amplifier 40 decides that electrons have been extracted from the floating gate, and outputs data "1" as the signal OUT.
This data reading operation is carried out based on, for example, a source voltage Vs=0 [V], a drain voltage Vd=1 [V] and a control gate voltage Vcg=5 [V].
Program Verification Operation:
In the program verification operation, a reading cell of the memory cell array 20 is selected at in a similar manner as in the data reading operation. However, different from the data reading operation, the reference word line driver 32 applies the program verification voltage generated by the program verification voltage generator 26 to the control gate of the reference cell 30. It should be noted that, the reading voltage generated by the reading voltage generator 24 is applied in the data reading operation.
The program verification voltage is lower than the reading voltage. When the signal SAIN becomes much smaller than the signal SAREF having a potential smaller than that during the data reading operation at a timing when the MOS transistor Tr15 is turned ON with the signal LT, the sense amplifier 40 decides that the program operation is carried out normally, and outputs data "0" as a signal OUT.
Erase Verification Operation:
In the erase verification operation, a reading cell of the memory cell array 20 is selected at in a similar manner as in the data reading operation. However, different from the data reading operation, the reference word line driver 32 applies the erase verification voltage generated by the erase verification voltage generator 28 to the control gate of the reference cell 30. It should be noted that, the reading voltage generated by the reading voltage generator 24 is applied in the data reading operation.
The erase verification voltage is larger than the reading voltage. When the signal SAIN becomes much larger than the signal SAREF having a potential larger than that during the data reading operation at a timing when the MOS transistor Tr15 is turned ON with the signal LT, the sense amplifier 40 decides that the erase operation is carried out normally, and outputs data "1" as a signal OUT.
As explained above, according to the conventional nonvolatile semiconductor memory device, verification operation is carried out by increasing or decreasing the voltage to be applied to the control gate of the reference cell 30 in comparison to the voltage applied during a normal data reading operation.
Thus, the program verification voltage generator 26 is required in the conventional nonvolatile semiconductor memory device for generating the program verification voltage and the erase verification voltage generator 28 is required for generating the erase verification voltage. Provision of these two voltage generators makes the circuit scale of the nonvolatile semiconductor memory device large and complex. Further, provision of these two voltage generators hinder the possibility of power saving.